Non-Volatile Memory (NVM) devices are subject to failures, such as word-line-to-word-line WL-WL short-circuit events. Several techniques for mitigating WL-WL short have been proposed. For example, U.S. Pat. No. 5,898,637, whose disclosure is incorporated herein by reference, describes a memory system that includes an array of memory cells connected along word lines and bit lines. A disclosed technique allows shorted word lines to be selected simultaneously during a programming operation, preliminary to an erase operation, to prevent the word-line supply from shorting to ground during the programming operation.
U.S. Pat. No. 8,730,722, whose disclosure is incorporated herein by reference, describes a technique that preserves data that would otherwise be lost in case of WL-WL short. Before writing a word line, the data from a previously written adjacent word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location.